Digital Fundamentals And Architecture,Nov-2009 Semester
1. The decimal equivalent of the octal number 13 is
a. D
b. 10
c. 11
d. None
1.0 Mark(s)
2. The gate that gives 1 output if any one of the input is 1, is
a. AND
b. NAND
c. XOR
d. None
1.0 Mark(s)
3. MOD 10 counter will count up to
a. 7
b. 8
c. 9
d. None
1.0 Mark(s)
4. With respect to Boolean Algebra, A.1 = ?
a. A
b. 1
c. 0
d. None
1.0 Mark(s)
5. 8085 has ___________ data lines.
a. 8
b. 16
c. 32
d. None
1.0 Mark(s)
6. MVI A, 55 H is an example for ___________ addressing mode.
a. Direct
b. Register
c. Immediate
d. None
1.0 Mark(s)
7. ___________ is used to eliminate the speed mismatch between processor and IO devices.
a. IO interface
b. Priority
c. Daisy chain
d. None
1.0 Mark(s)
8. ___________ is not an interrupt pin of 8085.
a. RST 7.5
b. ALE
c. INTR
d. TRAP
1.0 Mark(s)
9. How many address lines are needed to address a memory of size 8 KB?
a. 11
b. 12
c. 13
d. 14
1.0 Mark(s)
10. ___________ is a physical partition.
a. Page
b. Segment
c. DMA
d. None
1.0 Mark(s)
11. a. Draw the circuit of a Half Adder and give its truth table.
Or
b. Implement using fundamental gates.
5.0 Mark(s)
12. a. Draw the circuit of a 2 x 4 decoder.
Or
b. State and prove DeMorgan's theorems.
5.0 Mark(s)
13. a. Explain the Rotate instructions of 8085.
Or
b. What is multiplexing with respect to 8085?
5.0 Mark(s)
14. a. What is isolated I/O?
Or
b. Explain the interrupt mechanism.
5.0 Mark(s)
15. a. What is content addressable memory? Explain.
Or
b. Explain any one page replacement algorithm.
5.0 Mark(s)
16. a. Subtract 12 from 42 by using 1's complement and 2's complement methods.
Or
b. Draw the circuit of a parallel binary adder and explain its working.
8.0 Mark(s)
17. a. Simplify using Karnaugh map and implement using fundamental gates.
Q(A, B, C, D) = ?m(0, 1, 2, 5, 7, 9, 10, 11, 13, 14).
Or
b. Explain the functioning of a multiplexer with diagram.
8.0 Mark(s)
18. a. Discuss the internal architecture of 8085 with block diagram.
Or
b. Discuss the arithmetic instructions of 8085 with examples.
8.0 Mark(s)
19. a. What is meant by asynchronous data transfer? Explain.
Or
b. Discuss the parallel priority method of assigning priority to interrupts.
8.0 Mark(s)
20. a. Explain the match logic of associative memory.
Or
b. Discuss the cache memory concept with a diagram. What is its need?
8.0 Mark(s)
KEYWORDS:2009 BHARATHIAR UNIVERSITY B.C.A COMPUTER APPLICATION DIGITAL FUNDAMENTALS AND ARCHITECTURE,BHARATHIYAR UNIVERSITY QUESTION PAPER,BHARATHIAR UNIVERSITY,BHARATHIAR UNIVERSITY EXAM RESULTS,BHARATHIAR UNIVERSITY MBA,BHARATHIAR UNIVERSITY RESULTS,BHARATHIAR UNIVERSITY DISTANCE EDUCATION,BHARATHIAR UNIVERSITY SYLLABUS,BHARATHIAR UNIVERSITY MBA-CENTRE ,BHARATHIAR UNIVERSITY SCHEDULE OF EXAMINATIONS ,BHARATHIAR UNIVERSITY ADMISSION,BHARATHIAR UNIVERSITY COURSES,BHARATHIAR UNIVERSITY ACADEMIC, BHARATHIAR UNIVERSITY DEPARTMENTS,BHARATHIAR UNIVERSITY RESEARCH,BHARATHIAR UNIVERSITY MAIL,BHARATHIAR UNIVERSITY QUESTION PAPERS,BHARATHIAR UNIVERSITY COUNSELLING DATES,BHARATHIAR UNIVERSITY RE-EVALUATION RESULTS
1. The decimal equivalent of the octal number 13 is
a. D
b. 10
c. 11
d. None
1.0 Mark(s)
2. The gate that gives 1 output if any one of the input is 1, is
a. AND
b. NAND
c. XOR
d. None
1.0 Mark(s)
3. MOD 10 counter will count up to
a. 7
b. 8
c. 9
d. None
1.0 Mark(s)
4. With respect to Boolean Algebra, A.1 = ?
a. A
b. 1
c. 0
d. None
1.0 Mark(s)
5. 8085 has ___________ data lines.
a. 8
b. 16
c. 32
d. None
1.0 Mark(s)
6. MVI A, 55 H is an example for ___________ addressing mode.
a. Direct
b. Register
c. Immediate
d. None
1.0 Mark(s)
7. ___________ is used to eliminate the speed mismatch between processor and IO devices.
a. IO interface
b. Priority
c. Daisy chain
d. None
1.0 Mark(s)
8. ___________ is not an interrupt pin of 8085.
a. RST 7.5
b. ALE
c. INTR
d. TRAP
1.0 Mark(s)
9. How many address lines are needed to address a memory of size 8 KB?
a. 11
b. 12
c. 13
d. 14
1.0 Mark(s)
10. ___________ is a physical partition.
a. Page
b. Segment
c. DMA
d. None
1.0 Mark(s)
11. a. Draw the circuit of a Half Adder and give its truth table.
Or
b. Implement using fundamental gates.
5.0 Mark(s)
12. a. Draw the circuit of a 2 x 4 decoder.
Or
b. State and prove DeMorgan's theorems.
5.0 Mark(s)
13. a. Explain the Rotate instructions of 8085.
Or
b. What is multiplexing with respect to 8085?
5.0 Mark(s)
14. a. What is isolated I/O?
Or
b. Explain the interrupt mechanism.
5.0 Mark(s)
15. a. What is content addressable memory? Explain.
Or
b. Explain any one page replacement algorithm.
5.0 Mark(s)
16. a. Subtract 12 from 42 by using 1's complement and 2's complement methods.
Or
b. Draw the circuit of a parallel binary adder and explain its working.
8.0 Mark(s)
17. a. Simplify using Karnaugh map and implement using fundamental gates.
Q(A, B, C, D) = ?m(0, 1, 2, 5, 7, 9, 10, 11, 13, 14).
Or
b. Explain the functioning of a multiplexer with diagram.
8.0 Mark(s)
18. a. Discuss the internal architecture of 8085 with block diagram.
Or
b. Discuss the arithmetic instructions of 8085 with examples.
8.0 Mark(s)
19. a. What is meant by asynchronous data transfer? Explain.
Or
b. Discuss the parallel priority method of assigning priority to interrupts.
8.0 Mark(s)
20. a. Explain the match logic of associative memory.
Or
b. Discuss the cache memory concept with a diagram. What is its need?
8.0 Mark(s)
KEYWORDS:2009 BHARATHIAR UNIVERSITY B.C.A COMPUTER APPLICATION DIGITAL FUNDAMENTALS AND ARCHITECTURE,BHARATHIYAR UNIVERSITY QUESTION PAPER,BHARATHIAR UNIVERSITY,BHARATHIAR UNIVERSITY EXAM RESULTS,BHARATHIAR UNIVERSITY MBA,BHARATHIAR UNIVERSITY RESULTS,BHARATHIAR UNIVERSITY DISTANCE EDUCATION,BHARATHIAR UNIVERSITY SYLLABUS,BHARATHIAR UNIVERSITY MBA-CENTRE ,BHARATHIAR UNIVERSITY SCHEDULE OF EXAMINATIONS ,BHARATHIAR UNIVERSITY ADMISSION,BHARATHIAR UNIVERSITY COURSES,BHARATHIAR UNIVERSITY ACADEMIC, BHARATHIAR UNIVERSITY DEPARTMENTS,BHARATHIAR UNIVERSITY RESEARCH,BHARATHIAR UNIVERSITY MAIL,BHARATHIAR UNIVERSITY QUESTION PAPERS,BHARATHIAR UNIVERSITY COUNSELLING DATES,BHARATHIAR UNIVERSITY RE-EVALUATION RESULTS