UNIT II
ARITHMETIC UNIT
1.Give the symbol of a full adder circuit for a single stage addition
2.Give the representation for n bit ripple carry adder
3. Write down the Booth’s algorithm
4.What are the 2 ways to detect overflow in an n-bit adder?
Overflow can occur when the signs of two operands are the same. Overflow occurs when the carry bits Cn and Cn-1 are different.
5.What is the delay encountered for Cn-1, Sn-1 and Cn in the FA for a single stage
Cn-1 – 2(n-1)
Sn-1 – 2(n-1)+1
Cn – 2n
6.What is the delay encountered for all the sum bits in n-bit binary addition/subtraction logic unit?
The gate delays with and without overflow logic are 2n+2 and 2n respectively
7.Write down the basic generate and propagate functions for stage i
Gi = XiYi, Pi=Xi xor with Yi
8.Write down the general expression for Ci+1 using first level generate and propagate function
Ci+1 = Gi+PiGi-1+PiPi-1Gi-2+…+PiPi-1…P1G0+PiPi-1…P0G0
9.What are the two approaches to reduce delay in adders
§ Fastest electronic technology in implementing the ripple carry logic design
§ Augmented logic gate network
10.What is the delay encountered in the path in an n x n array multiplier
The delay encountered in the path in an n x n array multiplier is 6(n-1)-1
11.What is skipping over of one’s in Booth decoding?
The Transformation 011… 110= +100…0 – 10 is called skipping over one’s.In his case multiplier has its ones grouped into a few contiguous blocks.
12.What are the two attractive features of Booth algorithm
§ It handles both positive and negative multipliers uniformly
§ It achieves some efficiency in the number of additions required when the multiplier has a few large blocks of ones
13. Give an example for the worst case of Booth algorithm
The worst case is shown as below
In the worst case each bit of the multiplier selects the summands. This results in more number of summands.
14. What are the two techniques for speeding up the multiplication operation?
§ Bit Pair recoding
§ CSA
15. How bit pair recoding of multiplier speeds up the multiplication process?
It guarantees that the maximum number of summands that must be added is n/2 for nbit operands.
16. How CSA speeds up multiplication?
It reduces the time needed to add the summands. Instead of letting the carries ripple along the rows, they can be saved and introduced into the next row, at the correct
waited position.
17. Write down the levels of CSA steps needed to reduce k summands to two vectors
in CSA
The number of levels can be shown by 1.7log2k-1.7
18. Write down the steps for restoring division and non-restoring division
Non Restoring:
Step1: Do the following n times
1.If the sign of A is 0, shift A and Q left one bit position and subtract M from A otherwise shift A and Q left and add M to A.
2.Now if the sign of A is 0, set Q0 to 1; otherwise set Q0 to 0
Step 2: If the sign of A is 1, add M to A
Restoring:
§ Shift A and Q left one binary position
§ Subtract M from A
§ If the sign of A is one , set Q0 to 0, add M back to A otherwise set Q0 to 1
18.What is the advantage of non restoring over restoring division?
Non restoring division avoids the need for restoring the contents of register after
an successful subtraction.
19.What is the need for adding binary 8 value to the true exponential in floating point numbers?
This solves the problem of negative exponent.Due to this the magnitude of the
numbers can be compared.The excess-x representation for exponents enables efficient
comparison of the relative sizes of the two floating point numbers.
20.Briefly explain the floating point representation with an example?
The floating point representation has 3 fields
1.sign bit
2.significiant bits
3.exponent
For example consider 1.11101100110 x 10^5,
Mantissa=11101100110
Sign=0
Exponent=5
21.What are the 2 IEEE standards for floating point numbers?
1.single
2.double
22.What is overflow,underflow case in single precision(sp)?
Underflow-In SP it means that the normalized representation requires an exponent
less than -126.
Overflow- In SP it means that the normalized representation requires an exponent
greater than +127.
23.What are the exceptions encounted for FP operation?
The exceptions encounted for FP operation are overflow,underflow,/0,inexact
and invalid values.
24.What is guard bits?
Guard bits are extra bits which are produced during the intermediate steps to yield
maximum accuracy in the final results.
25.What are the ways to truncate guard bits?
1.Chopping
2.Von Neumann rounding
3.Rounding procedure
PART-B
1.Explain in detail the principle of Carry look ahead adder?
Generate function
Propagate function
4-bit carry look-ahead adder
2. Explain the sequential circuit binary multiplier and give an example for it.
Explanation
Diagram
3. Mention the rules for floating point addition and subtraction and explain how they are implemented ?
Rules
Diagram
Explanation
4. Multiply the following pair of signed 2’s complement number using Bit pair recoding of the multipliers.
A = 010111
B = 101100
5.Perform division on the following 5-bit unsigned integer using Restoring and
NonRestoring division: 10101 / 00101
6.Expalin 4X4 array multiplier . What is the delay in this case?
Explanation
Diagram
KEYWORDS:2009 ANNA UNIVERSITY CHENNAI B.E ELECTRONICS & COMMUNICATION ENGINEERING CS1251 (UNIT II) QUESTION BANK QUESTION PAPER,ANNA UNIVERSITY QUESTION PAPER,ANNA UNIVERSITY,ANNA UNIVERSITY CHENNAI,ANNA UNIVERSITY COIMBATORE,ANNA UNIVERSITY TRICHY,ANNA UNIVERSITY TIRUNELVELI,ANNA UNIVERSITY MADURAI,ANNA UNIVERSITY SYLLABUS,ANNA-UNIVERSITY RESULTS,ANNA UNIVERSITY DISTANCE EDUCATION,ANNA UNIVERSITY MBA-CENTRE FOR DISTANCE EDUCATION,ANNA UNIVERSITY SCHEDULE OF EXAMINATIONS,ANNA UNIVERSITY ADMISSION,ANNA UNIVERSITY COURSES,ANNA UNIVERSITY ACADEMIC,ANNA UNIVERSITY DEPARTMENTS,ANNA UNIVERSITY RESEARCH,ANNA UNIVERSITY MAIL,ANNA UNIVERSITY QUESTION PAPERS,ANNA UNIVERSITY COUNSELLING DATES,ANNA UNIVERSITY RE-EVALUATION RESULTS
ARITHMETIC UNIT
1.Give the symbol of a full adder circuit for a single stage addition
2.Give the representation for n bit ripple carry adder
3. Write down the Booth’s algorithm
4.What are the 2 ways to detect overflow in an n-bit adder?
Overflow can occur when the signs of two operands are the same. Overflow occurs when the carry bits Cn and Cn-1 are different.
5.What is the delay encountered for Cn-1, Sn-1 and Cn in the FA for a single stage
Cn-1 – 2(n-1)
Sn-1 – 2(n-1)+1
Cn – 2n
6.What is the delay encountered for all the sum bits in n-bit binary addition/subtraction logic unit?
The gate delays with and without overflow logic are 2n+2 and 2n respectively
7.Write down the basic generate and propagate functions for stage i
Gi = XiYi, Pi=Xi xor with Yi
8.Write down the general expression for Ci+1 using first level generate and propagate function
Ci+1 = Gi+PiGi-1+PiPi-1Gi-2+…+PiPi-1…P1G0+PiPi-1…P0G0
9.What are the two approaches to reduce delay in adders
§ Fastest electronic technology in implementing the ripple carry logic design
§ Augmented logic gate network
10.What is the delay encountered in the path in an n x n array multiplier
The delay encountered in the path in an n x n array multiplier is 6(n-1)-1
11.What is skipping over of one’s in Booth decoding?
The Transformation 011… 110= +100…0 – 10 is called skipping over one’s.In his case multiplier has its ones grouped into a few contiguous blocks.
12.What are the two attractive features of Booth algorithm
§ It handles both positive and negative multipliers uniformly
§ It achieves some efficiency in the number of additions required when the multiplier has a few large blocks of ones
13. Give an example for the worst case of Booth algorithm
The worst case is shown as below
In the worst case each bit of the multiplier selects the summands. This results in more number of summands.
14. What are the two techniques for speeding up the multiplication operation?
§ Bit Pair recoding
§ CSA
15. How bit pair recoding of multiplier speeds up the multiplication process?
It guarantees that the maximum number of summands that must be added is n/2 for nbit operands.
16. How CSA speeds up multiplication?
It reduces the time needed to add the summands. Instead of letting the carries ripple along the rows, they can be saved and introduced into the next row, at the correct
waited position.
17. Write down the levels of CSA steps needed to reduce k summands to two vectors
in CSA
The number of levels can be shown by 1.7log2k-1.7
18. Write down the steps for restoring division and non-restoring division
Non Restoring:
Step1: Do the following n times
1.If the sign of A is 0, shift A and Q left one bit position and subtract M from A otherwise shift A and Q left and add M to A.
2.Now if the sign of A is 0, set Q0 to 1; otherwise set Q0 to 0
Step 2: If the sign of A is 1, add M to A
Restoring:
§ Shift A and Q left one binary position
§ Subtract M from A
§ If the sign of A is one , set Q0 to 0, add M back to A otherwise set Q0 to 1
18.What is the advantage of non restoring over restoring division?
Non restoring division avoids the need for restoring the contents of register after
an successful subtraction.
19.What is the need for adding binary 8 value to the true exponential in floating point numbers?
This solves the problem of negative exponent.Due to this the magnitude of the
numbers can be compared.The excess-x representation for exponents enables efficient
comparison of the relative sizes of the two floating point numbers.
20.Briefly explain the floating point representation with an example?
The floating point representation has 3 fields
1.sign bit
2.significiant bits
3.exponent
For example consider 1.11101100110 x 10^5,
Mantissa=11101100110
Sign=0
Exponent=5
21.What are the 2 IEEE standards for floating point numbers?
1.single
2.double
22.What is overflow,underflow case in single precision(sp)?
Underflow-In SP it means that the normalized representation requires an exponent
less than -126.
Overflow- In SP it means that the normalized representation requires an exponent
greater than +127.
23.What are the exceptions encounted for FP operation?
The exceptions encounted for FP operation are overflow,underflow,/0,inexact
and invalid values.
24.What is guard bits?
Guard bits are extra bits which are produced during the intermediate steps to yield
maximum accuracy in the final results.
25.What are the ways to truncate guard bits?
1.Chopping
2.Von Neumann rounding
3.Rounding procedure
PART-B
1.Explain in detail the principle of Carry look ahead adder?
Generate function
Propagate function
4-bit carry look-ahead adder
2. Explain the sequential circuit binary multiplier and give an example for it.
Explanation
Diagram
3. Mention the rules for floating point addition and subtraction and explain how they are implemented ?
Rules
Diagram
Explanation
4. Multiply the following pair of signed 2’s complement number using Bit pair recoding of the multipliers.
A = 010111
B = 101100
5.Perform division on the following 5-bit unsigned integer using Restoring and
NonRestoring division: 10101 / 00101
6.Expalin 4X4 array multiplier . What is the delay in this case?
Explanation
Diagram
KEYWORDS:2009 ANNA UNIVERSITY CHENNAI B.E ELECTRONICS & COMMUNICATION ENGINEERING CS1251 (UNIT II) QUESTION BANK QUESTION PAPER,ANNA UNIVERSITY QUESTION PAPER,ANNA UNIVERSITY,ANNA UNIVERSITY CHENNAI,ANNA UNIVERSITY COIMBATORE,ANNA UNIVERSITY TRICHY,ANNA UNIVERSITY TIRUNELVELI,ANNA UNIVERSITY MADURAI,ANNA UNIVERSITY SYLLABUS,ANNA-UNIVERSITY RESULTS,ANNA UNIVERSITY DISTANCE EDUCATION,ANNA UNIVERSITY MBA-CENTRE FOR DISTANCE EDUCATION,ANNA UNIVERSITY SCHEDULE OF EXAMINATIONS,ANNA UNIVERSITY ADMISSION,ANNA UNIVERSITY COURSES,ANNA UNIVERSITY ACADEMIC,ANNA UNIVERSITY DEPARTMENTS,ANNA UNIVERSITY RESEARCH,ANNA UNIVERSITY MAIL,ANNA UNIVERSITY QUESTION PAPERS,ANNA UNIVERSITY COUNSELLING DATES,ANNA UNIVERSITY RE-EVALUATION RESULTS